ECE 33700 - ASIC Design Laboratory

Credit Hours: 2.00. Introduction to standard cell design of VLSI (Very Large Scale Integration) digital circuits using the VHDL hardware description language (Very High Speed Integrated Circuits Hardware Description Language). Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis, and testing. Typically offered Fall Spring.

Communication

Campus

Services

Other

ECE 33700 - ASIC Design Laboratory